1. Field of the Invention
This invention relates generally to processes for fabricating semiconductor devices having gate electrodes, and in particular to a new process for fabricating a deep-submicron metal-oxide semiconductor field effect transistor (MOSFET) with a gate having an increased effective gate length.
2. Description of the Prior Art
A Under conventional MOS manufacturing processes, transistors must be separated from each other to prevent operational interference and short circuits between them. This isolation is typically accomplished by providing a field oxide (FOX) region between transistors. A typical manufacturing process for making this field oxide region is the local oxidation of silicon (LOCOS) process. In this process, comparatively thick oxide layers, partly or wholly inset in the silicon substrate, may be obtained through the use of an oxidation-resistant silicon-nitride-containing masking layer.
As shown in the cross-section taken through a partial perspective view of a semiconductor device shown in FIG. 1A, an active area 12 is defined by a circumscribing field oxide region 10 after fabrication using the LOCOS process. A gate oxide layer 16, a polysilicon layer 18, and a phosphosilicate glass (PSG) layer 20 are sequentially deposited on top of the substrate 14 and the field oxide region 10.
Next, as sown in FIG. 1B, these layers are photolithographically patterned using well-known techniques not illustrated herein to define the gate structure 22 of what is to be a MOSFET device. The structure is subsequently subjected to a low-concentration N.sup.- /P.sup.- ion implantation process as suggested by the arrows 24. The structure is then heated in a thermal diffusion furnace and, as a result of heating and annealing, the implanted ions form lightly doped source and drain regions 26 and 28, respectively. Care is taken to insure that the concentrations of the implanted ions are sufficiently low to avoid the hot electron effect and the short channel effect in the lightly doped regions.
Next, as shown in FIG. 1C, a silicon nitride (Si.sub.3 N.sub.4) layer 30 is deposited on the structure and thereafter etched using an anisotropic etching process to form a vertically extending barrier 32 circumscribing the gate structure 22; see FIG. 1D. As illustrated in FIG. 1E, after the barrier 32 is formed, the remaining PSG layer 20 is selectively removed by the application of hydrofluoric acid (HF). Next, the structure is subjected to a high-concentration N.sup.+ /P.sup.+ ion implantation process as indicated by the arrows 34, and the device is again heated in a thermal diffusion furnace at approximately 900 to 1000.degree. C. to drive the implanted ions into the substrate 14 through the original source and drain regions 26 and 28 to form a heavily doped source 36 and a heavily doped drain 38. Note, however, that the N.sup.- regions beneath the barrier 32 survive as indicated at 26' and 28'. Meanwhile, the crystal structure of the surface regions of the silicon substrate damaged by the ion implantation process is restored through an annealing process.
Finally, as shown in FIG. 1F, a silicide layer 40 (e.g., a titanium silicide (TiSi.sub.x) layer), which covers the gate 18, the source 36 and the drain 38, is formed through vacuum deposition and rapid thermal nitridation (RTN) processes, thus completing the MOS manufacturing process.
Under the aforesaid conventional MOS manufacturing process, it is very difficult to generate a gate length of very fine dimensions. As known to those skilled in the art, the gate structure 22 in FIGS. 1B-1F is defined by a photoresist pattern of an equal length. As the critical dimensions of the semiconductor process technology become smaller and smaller, it becomes more and more difficult to build a photoresist pattern that would not easily peel off from the substrate during processing. This difficulty, if not resolved, would significantly limit the future development of deep sub-micron (e.g., quarter-micron or less) semiconductor structures.
Moreover, the aforesaid conventional technology utilizes ion implantation and thermal diffusion process to drive high-concentration ions into the substrate to form the source and drain. Because it is difficult to control the depth of implantation and diffusion, the ions may be diffused too deeply into the sub-micron MOS device, causing irreversible device defects and savaging the entire MOS manufacturing process.
Another significant disadvantage of the aforesaid conventional MOS manufacturing process is that it entails a difficult alignment task for the subsequent interconnection process because of the very narrow source-to-drain contact region.